# Controller adjustment To adjust the controller parameters the diagnostic values in file dcmlog0.0.csv can be used. The generation of logging information can be enabled setting bLogEnabled to `EC_TRUE` with the function [`emDcmConfigure()`](dcm_api.html.md#_CPPv414emDcmConfigure10EC_T_DWORDPK15EC_T_DCM_CONFIG10EC_T_DWORD). Controller log file description: | Column name | Description | |---------------------------|-------------------------------------------------------------------------------------| | Time[ms] | Controller execution timestamp | | SyncSetVal [ns] | Controller set value (distance between frame send time and SYNC0) | | BusTime [ns] | System Time | | BusTimeOff | System Time modulo Sync Cycle Time | | CtlAdj [ns] | Controller adjust value | | CtlErr [ns] | Controller error (EC_T_DCM_SYNC_NTFY_DESC.nCtlErrorNsecCur) | | CtlErrFilt | Filtered controller error | | Drift [ppm] | Drift between local clock and DC reference clock | | CtlErr [1/10 pmil] | For internal use only | | CtlOutSum | For internal use only | | CtlOutTot | For internal use only | | DCStartTime | DC start time send to the SubDevices to activate their SYNC signals | | DCMErrorCode | Current error code of the DCM controller (same value as returned by emDcmGetStatus) | | DCMInSync | Current InSync state of the DCM controller | | DCInSync | Current InSync state of the DC SubDevices | | SystemTimeDifference [ns] | Current system time difference of the DC SubDevice if monitoring is enabled | Log file analyze: To understand how the controller values correlates the following table can help: | Controller error | Drift | Reference-Clock | Output | |--------------------|---------------|-------------------|-------------------| | Positive | Must decrease | Must run faster | Double cycle time | | Negative | Must increase | Must run slower | Half cycle time | The DCM Controller reacts if the controller error is positive or negative. E.g. on a positive controller error (CtlErr ) the drift is too high and has to be decreased. Therefore the controller will speed up the reference clock. In some case the drift is too high (EcMasterDemoDc shows error messages) and cannot be balanced by the controller. This holds if the drift is higher than about 400ppm. Diagram 1: Bus offset in nanoseconds ![DCM Diagram 1 showing bus offset in nanoseconds over time, illustrating the controller's ability to converge the reference clock to the target offset](../Media/DCM_Diagram1.png) Diagram 2: Drift in ppm (part per million) ![DCM Diagram 2 showing drift in parts per million over time between the MainDevice local clock and the DC reference clock](../Media/DCM_Diagram2.png) Diagram 3: Controller error in nanoseconds ![DCM Diagram 3 showing controller error in nanoseconds during initial synchronization phase](../Media/DCM_Diagram3.png) Diagram 4: Controller error in steady state in nanoseconds ![DCM Diagram 4 showing controller error in nanoseconds in steady state after synchronization has stabilized](../Media/DCM_Diagram4.png) Troubleshooting: DCM BusShift needs a very deterministic and accurate time base. The following statements have to be true: - The timer input frequency must be determined with an accuracy greater than 600 ppm (333333 Hz vs 333000 Hz. E.g. at 1 ms, the cycle time must be between 999.400 µs and 1000.600 µs) - The timer frequency must never change after the application start On a PC platform the following settings have to be disabled in the BIOS. Be sure that these settings are really applied. - System management interrupt - Legacy USB support - Intel C-STATE tech - Intel Speedstep tech - Spread Spectrum