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EC-Master 5. Link Layer
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    • | EtherCAT manuals |
    • | www.developer.acontis.com |
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    • 1. Introduction
      • 1.1. What is EtherCAT?
      • 1.2. The EC-Master - Features
      • 1.3. Protected version
      • 1.4. License
    • 2. Getting Started
      • 2.1. EC-Master Architecture
      • 2.2. EtherCAT Network Configuration (ENI)
      • 2.3. Operating system configuration
      • 2.4. Running EcMasterDemo
      • 2.5. Compiling the EcMasterDemo
    • 3. Software Integration
      • 3.1. Network Timing
      • 3.2. Example application
      • 3.3. Master startup
      • 3.4. EtherCAT Network Configuration ENI
      • 3.5. Process Data Access
      • 3.6. Process Data Memory
      • 3.7. Error detection and diagnosis
      • 3.8. Trace Data
      • 3.9. EtherCAT Master Stack Source Code
    • 4. Platform and Operating Systems (OS)
      • 4.1. CMSIS-RTOS for STM32
      • 4.2. eCos
      • 4.3. tenAsys INtime
      • 4.4. Linux
      • 4.5. QNX Neutrino
      • 4.6. Renesas
      • 4.7. IntervalZero RTX
      • 4.8. SylixOS
      • 4.9. TI RTOS/SYSBIOS
      • 4.10. T-Kernel / eT-Kernel
      • 4.11. Windriver VxWorks
      • 4.12. Microsoft Windows
      • 4.13. Microsoft Windows CE
      • 4.14. Xenomai
      • 4.15. Zephyr
      • 4.16. FreeRTOS
      • 4.17. PC / BIOS
    • 5. Link Layer
      • 5.1. Link Layer initialization
      • 5.2. Intel Pro/1000 - emllI8254x
      • 5.3. Intel Pro/100 - emllI8255x
      • 5.4. Broadcom BcmGenet - emllBcmGenet
      • 5.5. Beckhoff CCAT - emllCCAT
      • 5.6. CMSIS-RTOS STM32Eth - emllCmsisEth
      • 5.7. Texas Instruments CPSW - emllCPSW
      • 5.8. DW3504 - emllDW3504
      • 5.9. Freescale TSEC / eTSEC - emllETSEC
      • 5.10. Freescale FslFec - emllFslFec
      • 5.11. Xilinx Zynq-7000/Ultrascale (GEM) - emllGEM
      • 5.12. Texas Instruments ICSS - emllICSS
      • 5.13. Texas Instruments ICSSG - emllICSSG on AM654x
      • 5.14. Microchip LAN743x - emlllan743x
      • 5.15. Windows NDIS - emllNdis
      • 5.16. Windows WinPcap - emllPcap
      • 5.17. RDC R6040 - emllR6040
      • 5.18. Realtek RTL8169 - emllRTL8169
      • 5.19. Renesas RZ/T1 - emllRZT1
      • 5.20. Renesas SHEth - emllSHEth
      • 5.21. VxWorks SNARF - emllSNARF
      • 5.22. Linux SockRaw - emllSockRaw
      • 5.23. Texas Instruments ICSSG via Ti FreeRTOS Enet LLD - emllTiEnetIcssg on AM64x
    • 6. Application programming interface, reference
      • 6.1. Generic API return status values
      • 6.2. Multiple EtherCAT Bus Support
      • 6.3. General functions
      • 6.4. Process Data Access
      • 6.5. Generic notification interface
      • 6.6. Slave control and status functions
      • 6.7. Diagnosis, error detection, error notifications
      • 6.8. Performance Measurement
      • 6.9. EtherCAT Mailbox Transfer
      • 6.10. Automation Device Specification over EtherCAT (AoE)
      • 6.11. CAN application protocol over EtherCAT (CoE)
      • 6.12. File access over EtherCAT (FoE)
      • 6.13. Servo Drive Profil according to IEC61491 over EtherCAT (SoE)
      • 6.14. Vendor specific protocol over EtherCAT (VoE)
      • 6.15. Raw command transfer
      • 6.16. EtherCAT Bus Scan
    • 7. RAS-Server for EC-Lyser and EC-Engineer
      • 7.1. Integration Requirements
      • 7.2. Pseudo Code
      • 7.3. Required API Calls
    • 8. Error Codes
      • 8.1. Groups
      • 8.2. Generic Error Codes
      • 8.3. DCM Error Codes
      • 8.4. ADS over EtherCAT (AoE) Error Codes
      • 8.5. CAN application protocol over EtherCAT (CoE) SDO Error Codes
      • 8.6. File Transfer over EtherCAT (FoE) Error Codes
      • 8.7. Servo Drive Profil over EtherCAT (SoE) Error Codes
      • 8.8. Remote API Error Codes

    5. Link Layer

    The EtherCAT master stack currently supports a variety of different Link Layer modules, each of which contained in a single library file, which is loaded by the core library dynamically. The EtherCAT master stack shipment consist of a master core library (e.g. EcMaster.dll for Windows, libEcMaster.a for Linux) and one (or more) libraries each containing support for one specific Link Layer module. Which library actually is loaded, is depending on the Link Layer parameters at runtime.

    The principle of the Link Layer selection is that the Link Layer name (Link Layer identification) is used to determine the location and name of a registration function called by the EtherCAT master and registers function pointers that allow access to the Link Layer functional entries.

    The EtherCAT Link Layer will be initialized using a Link Layer specific configuration parameter set. A pointer to this parameter set is part of the master’s initialization settings when calling the function emInitMaster()

    The EtherCAT master supports two Link Layer operating modes. If the Link Layer operates in interrupt mode all received Ethernet frames will be processed immediately in the context of the Link Layer receiver task. When using the polling mode the EtherCAT master will call the Link Layer receiver polling function prior to processing received frames.

    Optimized Link Layer drivers

    Optimized means operating directly on the network device’s register set instead of using the operating system’s native driver.

    Optimized Link Layer drivers and PHY OS Driver

    Some operating systems, e.g. Linux and Xenomai, provide drivers for most common Ethernet controllers and their related physical transceivers (PHY). The manufacturer specific PHY circuits can be handled by a dedicated driver. Using the PHY OS Driver interface it is possible to use the manufacturer’s dedicated PHY driver without modification of the acontis optimized Link Layer driver. Depending on the hardware architecture, an additional module from acontis, e.g. atemsys for Linux, grants access to the MDIO bus to the OS drivers, or request MDIO operations from the OS drivers.

    Note

    Link Layer modules not listed here may be available if purchased additionally. Not all Link Layer modules support interrupt mode.

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    © Copyright 2023-Sep-04, acontis technologies GmbH.
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