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EC-Master 5.1. Link Layer initialization
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    • 5. Link Layer
    • 1. Introduction
      • 1.1. What is EtherCAT?
      • 1.2. The EC-Master - Features
      • 1.3. Protected version
      • 1.4. License
    • 2. Getting Started
      • 2.1. EC-Master Architecture
      • 2.2. EtherCAT Network Configuration (ENI)
      • 2.3. Operating system configuration
      • 2.4. Running EcMasterDemo
      • 2.5. Compiling the EcMasterDemo
    • 3. Software Integration
      • 3.1. Network Timing
      • 3.2. Example application
      • 3.3. Master startup
      • 3.4. EtherCAT Network Configuration ENI
      • 3.5. Process Data Access
      • 3.6. Process Data Memory
      • 3.7. Error detection and diagnosis
      • 3.8. Trace Data
      • 3.9. EtherCAT Master Stack Source Code
    • 4. Platform and Operating Systems (OS)
      • 4.1. CMSIS-RTOS for STM32
      • 4.2. eCos
      • 4.3. tenAsys INtime
      • 4.4. Linux
      • 4.5. QNX Neutrino
      • 4.6. Renesas
      • 4.7. IntervalZero RTX
      • 4.8. SylixOS
      • 4.9. TI RTOS/SYSBIOS
      • 4.10. T-Kernel / eT-Kernel
      • 4.11. Windriver VxWorks
      • 4.12. Microsoft Windows
      • 4.13. Microsoft Windows CE
      • 4.14. Xenomai
      • 4.15. Zephyr
      • 4.16. FreeRTOS
      • 4.17. PC / BIOS
    • 5. Link Layer
      • 5.1. Link Layer initialization
      • 5.2. Intel Pro/1000 - emllI8254x
      • 5.3. Intel Pro/100 - emllI8255x
      • 5.4. Broadcom BcmGenet - emllBcmGenet
      • 5.5. Beckhoff CCAT - emllCCAT
      • 5.6. CMSIS-RTOS STM32Eth - emllCmsisEth
      • 5.7. Texas Instruments CPSW - emllCPSW
      • 5.8. DW3504 - emllDW3504
      • 5.9. Freescale TSEC / eTSEC - emllETSEC
      • 5.10. Freescale FslFec - emllFslFec
      • 5.11. Xilinx Zynq-7000/Ultrascale (GEM) - emllGEM
      • 5.12. Texas Instruments ICSS - emllICSS
      • 5.13. Texas Instruments ICSSG - emllICSSG on AM654x
      • 5.14. Microchip LAN743x - emlllan743x
      • 5.15. Windows NDIS - emllNdis
      • 5.16. Windows WinPcap - emllPcap
      • 5.17. RDC R6040 - emllR6040
      • 5.18. Realtek RTL8169 - emllRTL8169
      • 5.19. Renesas RZ/T1 - emllRZT1
      • 5.20. Renesas SHEth - emllSHEth
      • 5.21. VxWorks SNARF - emllSNARF
      • 5.22. Linux SockRaw - emllSockRaw
      • 5.23. Texas Instruments ICSSG via Ti FreeRTOS Enet LLD - emllTiEnetIcssg on AM64x
    • 6. Application programming interface, reference
      • 6.1. Generic API return status values
      • 6.2. Multiple EtherCAT Bus Support
      • 6.3. General functions
      • 6.4. Process Data Access
      • 6.5. Generic notification interface
      • 6.6. Slave control and status functions
      • 6.7. Diagnosis, error detection, error notifications
      • 6.8. Performance Measurement
      • 6.9. EtherCAT Mailbox Transfer
      • 6.10. Automation Device Specification over EtherCAT (AoE)
      • 6.11. CAN application protocol over EtherCAT (CoE)
      • 6.12. File access over EtherCAT (FoE)
      • 6.13. Servo Drive Profil according to IEC61491 over EtherCAT (SoE)
      • 6.14. Vendor specific protocol over EtherCAT (VoE)
      • 6.15. Raw command transfer
      • 6.16. EtherCAT Bus Scan
    • 7. RAS-Server for EC-Lyser and EC-Engineer
      • 7.1. Integration Requirements
      • 7.2. Pseudo Code
      • 7.3. Required API Calls
    • 8. Error Codes
      • 8.1. Groups
      • 8.2. Generic Error Codes
      • 8.3. DCM Error Codes
      • 8.4. ADS over EtherCAT (AoE) Error Codes
      • 8.5. CAN application protocol over EtherCAT (CoE) SDO Error Codes
      • 8.6. File Transfer over EtherCAT (FoE) Error Codes
      • 8.7. Servo Drive Profil over EtherCAT (SoE) Error Codes
      • 8.8. Remote API Error Codes

    5.1. Link Layer initialization

    The different Link Layer modules are selected and parameterized by a Link Layer specific structure. Each Link Layer specific structure start with a common EC_T_LINK_PARMS structure, followed by some Link Layer specific members. The common link parameter structure is passed to EC_T_INIT_MASTER_PARMS::pLinkParms with the call of emInitMaster() like in the following example:

    /* identify Link Layer in the common struture */
    oLinkParmsSockRaw.linkParms.dwSignature = EC_LINK_PARMS_SIGNATURE_SOCKRAW;
    oLinkParmsSockRaw.linkParms.dwSize = sizeof(EC_T_LINK_PARMS_SOCKRAW);
    OsStrncpy(&oLinkParmsSockRaw.linkParms.szDriverIdent, EC_LINK_PARMS_IDENT_SOCKRAW, EC_DRIVER_IDENT_MAXLEN);
    
    /* specific Link Layer parameters should be set here */
    
    /* pass Link Layer parameters */
    oInitMasterParms.dwSignature = ATECAT_SIGNATURE;
    oInitMasterParms.dwSize = sizeof(EC_T_INIT_MASTER_PARMS);
    oInitMasterParms.pLinkParms = &oLinkParmsSockRaw.linkParms;
    
    /* more parameters should be set here */
    
    /* initialize master */
    emInitMaster(dwInstanceId, &oInitMasterParms);
    
    struct EC_T_LINK_PARMS

    Public Members

    EC_T_DWORD dwSignature

    [in] Signature of the adapter specific structure containing the EC_T_LINK_PARMS structure

    EC_T_DWORD dwSize

    [in] Size of the adapter specific structure containing the EC_T_LINK_PARMS structure

    EC_T_LOG_PARMS LogParms

    [in] Logging parameters

    EC_T_CHAR szDriverIdent[EC_DRIVER_IDENT_NAMESIZE]

    [in] Name of Link Layer module (driver identification) for Link Layer Selection

    EC_T_DWORD dwInstance

    [in] Instance of the adapter. if EC_LINKUNIT_PCILOCATION is set: contains PCI address

    EC_T_LINKMODE eLinkMode

    [in] Mode of operation

    EC_T_CPUSET cpuIstCpuAffinityMask

    [in] Interrupt service thread CPU affinity mask

    EC_T_DWORD dwIstPriority

    [in] Task priority of the interrupt service task (not used in polling mode)

    enum EC_T_PHYINTERFACE

    Values:

    enumerator ePHY_UNDEFINED

    undefined

    enumerator ePHY_FIXED_LINK

    No PHY access at all

    enumerator ePHY_MII

    MII 10 / 100 MBit

    enumerator ePHY_RMII

    Reduced MII, 10 / 100 MBit

    enumerator ePHY_GMII

    Gigabit MII, 10, 100, 1000 MBit

    enumerator ePHY_SGMII

    Serial (SERDES) Gigabit MII, 10, 100, 1000 MBit

    enumerator ePHY_RGMII

    Reduced Gigabit MII, 10, 100, 1000 MBit

    enumerator ePHY_OSDRIVER

    Get interface type from OS

    enumerator ePHY_RMII_50MHZ

    ePHY_RMII with 50 MHz clock mode

    struct EC_T_LINK_TTS

    Public Members

    EC_T_BOOL bEnabled

    [in] Use Time-Triggered Send

    EC_T_DWORD dwCycleTimeUsec

    [in] Cycle time between 2 pfnStartCycle calls

    EC_T_DWORD dwSendOffsetUsec

    [in] Time between pfnStartCycle call and frame transmission

    EC_T_LINK_TTS_CALLBACK pfnStartCycle

    [in] Callback function called cyclically according dwCycleTimeUsec

    EC_T_VOID *pvStartCycleContext

    [in] Context passed to each pfnTtsStartCycle call

    5.1.1. Link Layer instance selection via PCI location

    For some operating systems it is possible to address the Link Layer instance using its PCI address as an alternative. To do this, EC_LINKUNIT_PCILOCATION (0x01000000) and the PCI location must be set as EC_T_LINK_PARMS::dwInstance.

    On Linux the PCI address can be shown using e.g.:

    lspci | grep Ethernet
    
    00:19.0 Ethernet controller: Intel Corporation Ethernet Connection I217-LM (rev 04)
    04:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
    05:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
    

    The format of EC_T_LINK_PARMS::dwInstance using PCI bus address is:

    0x01bbddff
    • bb Bus Number

    • dd Device Number

    • ff Function Number

    EC_T_LINK_PARMS::dwInstance = 0x01001900; //"0000:00:19.0"
    

    On Windows the integer value displayed in properties dialog must be converted to HEX. E.g the number from the following dialog (PCI bus 11, device 0, function 0) corresponds to 0x010B0000 (bus 0x0B).

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    © Copyright 2023-Sep-04, acontis technologies GmbH.
    Created using Sphinx 4.2.0. and Material for Sphinx