5.11. Xilinx Zynq-7000/Ultrascale (GEM) - emllGEM

The parameters to the GEM Link Layer are setup-specific. The function CreateLinkParmsFromCmdLineGEM() in EcSelectLinkLayer.cpp demonstrates how to initialize the Link Layer instance.

struct EC_T_LINK_PARMS_GEM

Public Members

EC_T_LINK_PARMS linkParms

Common link parameters. Signature must be set to EC_LINK_PARMS_SIGNATURE_GEM

EC_T_GEM_RXSOURCE eRxSource

Source of RX clock, control and data signals

EC_T_DWORD dwPhyAddr

PHY address

EC_T_DWORD dwRxInterrupt

Receive interrupt number (IRQ)

EC_T_BOOL bUseDmaBuffers

Use buffers from DMA (EC_TRUE) or from heap for receive. AllocSend is not supported, when EC_FALSE.

EC_T_BOOL bNoPhyAccess

EC_FALSE: Link layer should initialize PHY and read link status (connected/disconnected). EC_TRUE: Client is responsible of PHY initialization and clock initialization

EC_T_BOOL bUseGmiiToRgmiiConv

Use XILINX GMIITORGMII Converter (EC_TRUE)

EC_T_DWORD dwConvPhyAddr

PHY address used to communicate with converter. In Linux doc it named “reg”

EC_T_DWORD dwTxDmaDesCnt

Transmit DMA descriptor buffer count. Must be a power of 2, maximum 256

EC_T_DWORD dwRxDmaDesCnt

Receive DMA descriptor buffer count. Must be a power of 2, maximum 256

EC_T_GEM_TYPE eGemType

System on Chip type

EC_T_PHYINTERFACE ePhyInterface

PHY connection type

EC_T_BOOL bNoPinMuxing

No clock configuration and pin muxing

EC_T_GEM_CLK_DIV_TYPE eClkDivType

Change Ref Clock settings

EC_T_BOOL bNotUseCacheSync

Default use of CacheSync EC_FALSE, Don’t call CacheSync on older systems EC_TRUE

enum EC_T_GEM_RXSOURCE

Values:

enumerator eGemRxSource_MIO

MIO as source for RX clock, control and data signals

enumerator eGemRxSource_EMIO

EMIO as source for RX clock, control and data signals

enum EC_T_GEM_TYPE

Values:

enumerator eGemType_Zynq7000

Xilinx Zynq 7000

enumerator eGemType_ZynqUltrascale

Xilinx Zynq Ultrascale