5.10. Xilinx Zynq-7000/Ultrascale (GEM)

The parameters to the GEM Link Layer are setup-specific. The function “CreateLinkParmsFromCmdLineGEM” in EcSelectLinkLayer.cpp demonstrates how to initialize the Link Layer instance.

Public Members

Common link parameters. Signature must be set to EC_LINK_PARMS_SIGNATURE_GEM

Source of RX clock, control and data signals

PHY address

Receive interrupt number (IRQ)

Use buffers from DMA (EC_TRUE) or from heap for receive. AllocSend is not supported, when EC_FALSE.

EC_FALSE: Link layer should initialize PHY and read link status (connected/disconnected). EC_TRUE: Client is responsible of PHY initialization and clock initialization

Use XILINX GMIITORGMII Converter (EC_TRUE)

PHY address used to communicate with converter. In Linux doc it named “reg”

Transmit DMA descriptor buffer count. Must be a power of 2, maximum 256

Receive DMA descriptor buffer count. Must be a power of 2, maximum 256

System on Chip type

PHY connection type

enum EC_T_GEM_RXSOURCE

Values:

enumerator eGemRxSource_MIO

MIO as source for RX clock, control and data signals

enumerator eGemRxSource_EMIO

EMIO as source for RX clock, control and data signals

enumerator eGemRxSource_BCppDummy
enum EC_T_GEM_TYPE

Values:

enumerator eGemType_Zynq7000

Xilinx Zynq 7000

enumerator eGemType_ZynqUltrascale

Xilinx Zynq Ultrascale

enumerator eGemType_BCppDummy