5.8. Freescale TSEC / eTSEC - emllETSEC

The parameters to the ETSEC Link Layer are setup-specific. The function “CreateLinkParmsFromCmdLineETSEC” in EcSelectLinkLayer.cpp demonstrates how to initialize the Link Layer instance.

Public Members

Common link parameters. Signature must be set to EC_LINK_PARMS_SIGNATURE_ETSEC

Physical base address of register block (4k)

Physical base address of local MDIO register block (4k). For the eTSEC V1 or TSEC this is the same as dwRegisterBase, for the eTSEC V2 it’s not.

Physical base address of MDIO register block (4k). This is the MDIO base of the (e)TSEC where the PHY (MII bus) is physically connected to (MII interface is shared by (e)TSEC’s).

PHY address on MII bus. ETSEC_FIXED_LINK if fixed link configuration

Address of internal TBI phy. Any address from [0..31] can be used here, but the address shouldn’t collide with any external PHY connected to the external MII bus

Only evaluated if dwPhyAddr == FIXED_LINK. Set to one of the ETSEC_LINKFLAG_* macros. I.e. ETSEC_LINKFLAG_1000baseT_Full

MAC address

This mutex protect the access to the (shared) MII bus. Set to 0 if mutex shouldn’t be used. The MII bus is shared between eTSEC instances. So this mutex should be created once and assigned here for all Linklayer instances

Receive interrupt number (IRQ)

EC_TRUE: copy buffer before processing, EC_FALSE: Use buffers from DMA (default)

System on Chip type

Full control over the MAC and need to initialize MAC and the connections to the PHYs



enumerator eETSEC_P2020RDB

MAC on Freescale P2020

enumerator eETSEC_TWRP1025

MAC on Freescale TWRP1025

enumerator eETSEC_ISTMPC8548

MAC on Freescale ISTMPC8548

enumerator eETSEC_XJ_EPU20C

MAC on Freescale XJ EPU20C

enumerator eETSEC_TWRLS1021A

MAC on Freescale TWRLS1021A

enumerator eETSEC_TQMLS_LS102XA

MAC on Freescale TQMLS LS102XA

5.8.1. ETSEC supported MAC’s

  • TSEC (not tested): Legacy hardware. Should be supported, because eTSEC is compatible to TSEC if the enhanced functionality is not used.

  • eTSEC v1 (tested): This chip is used for QorIQ (i.e. P2020E) and PowerQUICC devices (i.e. MPC8548). It has 4k of IO memory.

  • eETSEC v2, also called vETSEC, v read as “virtualization” (tested): This chip is used for newer QorIQ devices (i.e. P1020). It has 12k of IO memory (4k MDIO, 4k Register group0, 4k Register group1)

5.8.2. Shared MII bus

The driver will access the Ethernet PHY for the following reasons:

  • Check for link (or timeout), if the driver instance is opened.

  • Configure MAC according to the auto-negotiated PHY speed (mandatory).

  • Check link (and reconfigure MAC) during cyclic run. Therefore EC_LINKIOCTL_UPDATE_LINKSTATUS should not be called explicitly in parallel!


The external PHYs are connected physically to the MII bus of the first eTSEC (and/or eTSEC3, depending on SoC type). From SoC reference manuals: “ MII Management Configuration Register (MIIMCFG) … Note that MII management hardware is shared by all eTSECs. Thus, only through the MIIM registers of eTSEC1 can external PHYs be accessed and configured.”

That means that the acontis TSEC / eTSEC driver will also mmap the register set of the corresponding eTSEC. The following initialization parameters are used to specify the MII settings:

  1. Memory map of eTSEC which will manage the MII bus (connection of external PHY’s):

poDrvSpecificParam->dwPhyMdioBase = dwCcsrbar + 0x24000;
  1. Dummy address assigned to internal TBI PHY. Use any address (from 0 .. 31) which will not collide with any of the physical PHY’s addresses:

poDrvSpecificParam->dwTbiPhyAddr = 16;

5.8.3. Locking

The optional lock is acquired each time the MDIO register (specified by poDrvSpecificParam->dwPhyMdioBase) are accessed:

poDrvSpecificParam->oMiiBusMtx = EC_NULL;

/* implement locking by using return value of LinkOsCreateLock(eLockType_DEFAULT); */